My research spans the full stack — device physics at the bottom, circuits in the middle, systems at the top. Working across the layers is the point: a device is only as useful as the circuit that reads it, and an architecture only as honest as the device model underneath it.
Devices — metal-oxide RRAM and memristors (NbOₓ, HfOₓ, TaOₓ), 2D-material FETs (MoS₂, WS₂, WSe₂, black phosphorus), graphene photodetectors. Circuits — crossbar array architectures, compact modeling in Verilog-A, analog and mixed-signal ICs in 65/130-nm CMOS. Systems — neuromorphic and in-memory computing that keeps computation where the data lives.
Physics-based modeling of metal-oxide memristors — NbOₓ, HfOₓ, TaOₓ — capturing how heat and geometry shape switching behavior. Better device models mean memory cells that switch predictably, selectors that actually select, and synaptic elements circuit designers can trust.
Crossbar arrays let computation happen where data already lives, removing the energy cost of shuttling bits to a processor. My work attacks the practical barriers — sneak currents, readout margin, array-level power — through device-circuit co-design rather than device physics alone.
As silicon channels shrink below 10 nm, atomically thin semiconductors — MoS₂, WS₂, WSe₂, black phosphorus, graphene — become serious candidates. I use quantum-transport simulation to project how these devices perform, then distill the physics into compact models circuit designers can actually use.
The layer where device insight becomes silicon. From OTAs and baseband filters in 65-nm to AGC amplifiers in 130-nm CMOS, and now clocking, timing, and ATE design in industry — this is where models meet layout, corners, and measurement.
Numbered in the order they tell the story: from a memristor film, to an array, to a transistor that doesn't exist yet, to an amplifier that does.
My B.Tech capstone at IIT Ropar, carried out fully independently. I built a COMSOL physics model of a niobium-oxide self-selective memristor, abstracted it into a Verilog-A compact model, and simulated large-scale crossbars in Cadence Spectre. A modified array architecture mitigates sneak current while improving power, readout margin, and area. The work became a first-author journal paper in Memories — Materials, Devices, Circuits and Systems (2023). See Publications
A systematic study of how thermal conditions and device geometry govern resistive switching in three metal-oxide RRAM systems, modeled in COMSOL. The simulations tie switching metrics directly to heat generation and dissipation inside the active layer — explaining why the same material behaves differently across stacks. Presented as an oral talk at MEMRISYS 2021, Tsukuba. See Publications
Quantum-transport analysis of MoS₂, WS₂, WSe₂, and black-phosphorus FETs at sub-10-nm channel lengths, using an NEGF solver written in MATLAB. The device physics was distilled into Verilog-A compact models, enabling static and dynamic CMOS-inverter analysis in Cadence Spectre — a projection of how 2D-material logic performs where silicon runs out of room. Published in IEEE Transactions on Electron Devices (2021). See Publications
An NEGF quantum-transport solver built from scratch in MATLAB and applied to graphene-nanoribbon and bilayer-graphene FETs. The solver captures band structure, electrostatics, and ballistic transport self-consistently, providing a platform for exploring how graphene-derived channel materials behave as transistors rather than as wonder materials.
Summer research at the Chinese University of Hong Kong with Prof. Hon Ki Tsang's group: numerical modeling of carrier diffusion in high-speed graphene-on-Si₃N₄ waveguide photodetectors. I built ambipolar drift-diffusion and band models in MATLAB, extracted a Verilog-A device model, and matched Cadence Spectre simulations against experimental data — pinning down what limits detector speed. See Experience
A feedback automatic-gain-control amplifier for wireless receivers, designed at the University of Michigan in Prof. Ehsan Afshari's course. The loop holds the output constant across a 60 dB input dynamic range (0.3 µV–300 µV) — a full analog-design exercise from topology choice through loop dynamics and transistor-level verification in Cadence.
Eight peer-reviewed publications — journal articles and conference papers on memristors, crossbar architectures, and 2D-material devices, with DOI links and citation details.