Experience

Analog and mixed-signal circuit design on the ATE team — the automated test equipment that measures, stresses, and validates other silicon. The role continues a through-line of high-accuracy analog design, now applied to test and measurement at production scale.

Designing and verifying low-jitter clocking and timing circuits for space and high-performance compute applications, owning blocks from concept to silicon sign-off. Design verification of a PCIe Gen 6 reference clock generator and a 20-output clock buffer across PVT and Monte Carlo.

Summer internship during the M.S. at Michigan, with work spanning device physics and analog layout.

Research with Dr. Mehdi Saligane on a project sponsored by NIST and Google: peripheral circuitry design for the characterization and testing of novel neuromorphic and memory devices.

Assumed full responsibility for developing the prototype — PCB design, Raspberry Pi and sensor integration — for head-up displays used to show advertisements on the passenger windows of cars.

Full-flow analog design for a 5G semiconductor startup: an OTA with trickle bias in 65-nm CMOS taken through layout and DRC/LVS sign-off; 3rd- and 5th-order Chebyshev active-RC baseband filters across 5G bandwidth modes; the company's IBIS modeling toolkit built from S2IBIS; and top-level simulation of the analog–RF transmit chain.

Summer research in Prof. Hon Ki Tsang's lab at the Chinese University of Hong Kong: numerical modeling of carrier diffusion in high-speed graphene-on-Si₃N₄ waveguide photodetectors, from MATLAB transport models to a Verilog-A device model validated in Cadence Spectre.

Two years in Dr. Brajesh Rawat's nanoelectronics lab: metal-oxide RRAM device modeling with crossbar-level simulation, and compact modeling of 2-D transition-metal-dichalcogenide FETs using NEGF quantum transport, Verilog-A compact models, and Cadence Spectre circuit analysis.